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UHP112 Two-Port PCI-to-USB OpenHCI Host Controller - Product Brief
Features
32-bit, 33 MHz PCI interface compliant with PCI Local Bus Specification Revision 2.1s Two downstream USB ports Full compliance with Universal Serial Bus Specification Revision 1.1 OpenHCI Open Host Controller Interface Specification for USB Release 1.0a compatible Provides advanced power management capabilities compliant with PCI Bus Power Management Interface Specification Revision 1.1 Fully compatible with Microsoft Windows* Standard OpenHCD Drivers Supports legacy keyboard and mouse devices Integrated dual-speed USB transceivers 3 V or 5 V switchable PCI signaling 100-pin TQFP Evaluation kit available The UHP112 is a 3.3 V device fabricated in 0.35 m technology. Integrated dual-speed USB transceivers enable a single-chip PCI-to-USB solution. The UHP112 supports the legacy peripherals feature, as defined in the OpenHCI Specification Release 1.0a. An advanced power management capabilities interface compliant with PCI Bus Power Management Interface Specification Revision 1.1 is present to offer a variety of power-savings modes to the host system. The UHP112 provides two downstream USB ports for connectivity with any USB compliant device or hub. Full-speed or low-speed peripherals are supported along with all of the USB transfer types: control, interrupt, bulk, or isochronous. The UHP112's OpenHCI compliance offers significant USB performance benefits and reduced CPU overhead compared to other host controllers. The UHP112 is fully compatible with the Microsoft Windows Standard OpenHCD Drivers. The UHP112 is supported natively as an OHCI compliant host controller under Windows 98, ME, XP and CE, as well as under MacOS and Linux. For customers using other operating systems, SoftConnex Technologies' USBLink Host solution supports a wide range of products, such as AMX, ITRON, Linux, LynxOS, MS-DOS, Nucleus, OS-40, PowerTV, QNX, ThreadX, VRTX and VxWorks. USBLink Host is also distinguished by the variety of USB devices that it can support, including: printers; audio, communication, human interface and mass storage devices; digital still and video cameras; Hubs; MP3 players; Host to Host cables and Bluetooth connectivity products. In addition, USBLink Host runs on both little endian (x86, ARM, SA, SH, ST) and big endian (PPC, MIPS) processors. For more information, please visit www.softconnex.com.
Applications
Seamless integration with 3 V or 5 V PCI-based computer products Supports all USB compliant devices and hubs
Description
The Transdimension's UHP112 provides a singlechip PCI-to-Universal Serial Bus (USB) solution. The UHP112 interfaces directly to any 32-bit 33 MHz PCI bus and is ideal for either onboard applications or add-in card applications. It can easily be configured to communicate in either a 3 V PCI environment or 5 V PCI environment simply by selecting the appropriate communications voltage level on the VIO input pin.
* Microsoft and Windows are registered trademarks of Microsoft Corporation.
*SoftConnex Technologies is a wholly owned subsidiary of Transdimension Inc.
UHP112 Two-Port PCI-to-USB OpenHCI Host Controller
Description (continued)
UHP112 PCI-TO-USB OpenHCI HOST CONTROLLER ROM BIOS MASTER FIFOs ADDRESS W DATA ADDRESS/ DATA MUX DATA R DATA ADDRESS ADDRESS R DATA W DATA PCI BUS GLUE SLAVE FIFOs IDSEL CONFIG. BLOCK PCI SLAVE CONTROL PCI MASTER CONTROL PCI CONTROL INTA INTR. BLOCK F-BUS CONTROL ADDRESS DATA DATA CONTROL DATA HCI CONTROL CONTROL USB SLAVE STATE BLOCK CONTROL OHCI REG CONTROL DATA DATA ADDRESS/ DATA CONTROL HCI MASTER BLOCK STATUS DATA DATA CONTROL LIST PROCESSOR CONTROL BLOCK ED AND TD REGS STATUS 64 x 8 FIFO CONTROL DATA ADDRESS DATA CONTROL DATA DATA HSIE S/M DPLL RX ROOT HUB AND HOST SIE CLOCK MUX 12/1.5
ADDRESS/ DATA PARITY
OHCI ROOT HUB PORT 1 PORT 2
TX
USB
USB
FIFO STATUS
F-BUS IRQ
FIFO 64 x 8
5-5596.b
Figure 1. UHP112 Interconnection Diagram
Applicable Documents and Specifications
PCI Local Bus Specification Revision 2.1s., June 1, 1995. PCI Special Interest Group. Universal Serial Bus Specification Revision 1.1., September 23, 1998. Compaq/Digital Equipment Corporation/ IBM PC Company/Intel/Microsoft/NEC/Northern Telecom. OpenHCI Open Host Controller Interface Specification for USB Release 1.0a., July 31, 1997. Compaq/Microsoft/ National Semiconductor. PCI Bus Power Management Interface Specification Revision 1.1., December 18, 1998. PCI Special Interest Group.
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Transdimension Inc.
UHP112 Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
AD3 AD4 VDD KIRQ1I VSS AD5 AD6 AD7 VDD VIO VSS C/BEN0 AD8 AD9 AD10 VSS AD11 AD12 AD13 VDD VSS AD14 AD15 C/BEN1 PAR
100 99 98 97 96 95 26 27 28 29 30 31 32 33 34 35 36 37 38
VDD5 IRQ1 IRQ12 SMIN INTAN RSTN CLK VSS VDD GNTN REQN AD31 AD30 AD29 VSS VDD AD28 AD27 AD26 AD25 VDD VSS AD24 C/BEN3 IDSEL
39 40 41 42 43 44 45 46 47 48 49 50
A20MN AD2 AD1 AD0 VSS CLK48 VDD PMEN PRTPWR1 PWRFLT1N PWROK1 VDDT DPLS1 DMNS1 PMIENABLE VSST VDDT DPLS2 DMNS2 VSS TEST0 PWROK2 PWRFLT2N PRTPWR2 TEST1
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TDUHP112
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SERRN VDD MIRQ12I VSS PERRN STOPN DEVSELN TRDYN IRDYN VSS VDD FRAMEN C/BEN2 AD16 AD17 VDD VSS AD18 AD19 AD20 AD21 VSS A20I AD22 AD23
5-7220a
Figure 2. Pin Diagram (100-Pin TQFP)
Transdimension Inc.
3
UHP112 Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 1. Numeric Pin Cross Reference Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Symbol* A20MN AD2 AD1 AD0 VSS CLK48 VDD PMEN PRTPWR1 PWRFLT1N PWROK1 VDDT DPLS1 DMNS1 PMIENABLE VSST VDDT DPLS2 DMNS2 VSS TEST0 PWROK2 PWRFLT2N PRTPWR2 TEST1 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol* VDD5 IRQ1 IRQ12 SMIN INTAN RSTN CLK VSS VDD GNTN REQN AD31 AD30 AD29 VSS VDD AD28 AD27 AD26 AD25 VDD VSS AD24 C/BEN3 IDSEL Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Symbol* AD23 AD22 A20I VSS AD21 AD20 AD19 AD18 VSS VDD AD17 AD16 C/BEN2 FRAMEN VDD VSS IRDYN TRDYN DEVSELN STOPN PERRN VSS MIRQ12I VDD SERRN Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol* PAR C/BEN1 AD15 AD14 VSS VDD AD13 AD12 AD11 VSS AD10 AD9 AD8 C/BEN0 VSS VIO VDD AD7 AD6 AD5 VSS KIRQ1I VDD AD4 AD3
* Active-low signals within this document are indicated by an N following the symbol names.
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Transdimension Inc.
UHP112 Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 2. Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Symbol* A20MN AD2 AD1 AD0 VSS CLK48 VDD PMEN PRTPWR1 PWRFLT1N PWROK1 VDDT DPLS1 DMNS1 PMIENABLE VSST VDDT DPLS2 DMNS2 VSS TEST0 Type Output/Open Drain Bidir Bidir Bidir Power Input Power Output/Open Drain Bidir Input Input Power Bidir Bidir Input Power Power Bidir Bidir Power Input Description Legacy Gate A20 Output (Active-Low). PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Device Ground. USB Clock (48 MHz). Device Power (3.3 V). Power Management Event (Active-Low). Port 1 Power. Logic output expected to turn on port 1 power. Bootstrap low for high active. Bootstrap high for low active. Port 1 Power Fault (Active-Low). Logic input indicates an overcurrent fault on port 1. Port 1 Power OK. Analog or digital input to inform the UHP112 that USB port 1 power is stable (when >4 V). Transceiver Power (3.3 V). DIfferential USB Port 1 Signals. Power Management Interface Enable Input (Active-High). Transceiver Ground. Transceiver Power (3.3 V). Differential USB Port 2 Signals. Device Ground. Test 0. For device testing. Connect this to ground during normal use. Connect to logic high for NAND tree mode. See NAND Tree Mode on page 2-32. Port 2 Power OK. Analog or digital input to inform the UHP112 that USB port 2 power is stable (when >4 V). Port 2 Power Fault (Active-Low). Logic input indicates an overcurrent fault on port 2. Port 2 Power. Logic output expected to turn on port 2 power. Bootstrap low for high active. Bootstrap high for low active. Test 1. For device testing. Tie this to ground during normal use. Connect to logic high for NAND tree mode. See the NAND Tree Mode section on page 2-32. 5 V Power for 5 V PCI Operation. 5 V must be present on this pin while selecting either 3 V PCI or 5 V PCI operation with the VIO pin. See PCI Connection Instructions section on page 2-26. System Keyboard Interrupt (Active-High). System Mouse Interrupt (Active-High). System Management Interrupt (Active-Low). PCI Interrupt (Active-Low). PCI Reset (Active-Low). Also the chip reset. PCI Clock. 33 MHz input clock. 5
22 23 24 25
PWROK2 PWRFLT2N PRTPWR2 TEST1
Input Input Bidir Input
26
VDD5
Power
27 28 29 30 31 32
IRQ1 IRQ12 SMIN INTAN RSTN CLK
Output/Open Drain Output/Open Drain Output/Open Drain Output/Open Drain Input Input
* Active-low signals within this document are indicated by an N following the symbol names.
Transdimension Inc.
UHP112 Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Symbol* VSS VDD GNTN REQN AD31 AD30 AD29 VSS VDD AD28 AD27 AD26 AD25 VDD VSS AD24 C/BEN3 IDSEL AD23 AD22 A20I VSS AD21 AD20 AD19 AD18 VSS VDD AD17 AD16 C/BEN2 FRAMEN VDD VSS IRDYN TRDYN DEVSELN STOPN PERRN VSS MIRQ12I VDD Type Power Power Input Output/3-State Bidir Bidir Bidir Power Power Bidir Bidir Bidir Bidir Power Power Bidir Bidir Bidir Bidir Bidir Input Power Bidir Bidir Bidir Bidir Power Power Bidir Bidir Bidir Bidir Power Power Bidir Bidir Bidir Bidir Bidir Power Input Power Description Device Ground. Device Power (3.3 V). PCI Grant Signal (Active-Low). PCI Request Signal (Active-Low). PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Device Ground. Device Power (3.3 V). PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Device Power (3.3 V). Device Ground. PCI Address/Data Bit. PCI Command/Byte Enable. PCI ID Select. PCI Address/Data Bit. PCI Address/Data Bit. Legacy Gate A20 Input. Device Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Device Ground. Device Power (3.3 V). PCI Address/Data Bit. PCI Address/Data Bit. PCI Command/Byte Enable. PCI Frame (Active-Low). Device Power (3.3 V). Device Ground. PCI Initiator Ready (Active-Low). PCI Target Ready (Active-Low). PCI Device Select (Active-Low). PCI Stop (Active-Low). PCI Parity Error (Active-Low). Device Ground. Legacy Mouse Controller Interrupt Input. Device Power (3.3 V).
* Active-low signals within this document are indicated by an N following the symbol names.
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Transdimension Inc.
UHP112 Two-Port PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pin 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Symbol* SERRN PAR C/BEN1 AD15 AD14 VSS VDD AD13 AD12 AD11 VSS AD10 AD9 AD8 C/BEN0 VSS VIO Type Output/Open Drain Bidir Bidir Bidir Bidir Power Power Bidir Bidir Bidir Power Bidir Bidir Bidir Bidir Power Power Description PCI System Error (Active-Low). PCI Parity. PCI Command/Byte Enable. PCI Address/Data Bit. PCI Address/Data Bit. Device Ground. Device Power (3.3 V). PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Device Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Command/Byte Enable. Device Ground. Voltage I/O. This signal is used to indicate to the UHP112 the PCI signaling interface to use (3 V or 5 V PCI signaling). A 3 V on VIO will indicate 3 V PCI signaling while 5 V on VIO will indicate 5 V PCI signaling. This pin may be connected directly to the PCI VIO signal. Device Power (3.3 V). PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Device Ground. Legacy Keyboard Controller Interrupt Input. Device Power (3.3 V). PCI Address/Data Bit. PCI Address/Data Bit.
92 93 94 95 96 97 98 99 100
VDD AD7 AD6 AD5 VSS KIRQ1I VDD AD4 AD3
Power Bidir Bidir Bidir Power Input Power Bidir Bidir
* Active-low signals within this document are indicated by an N following the symbol names.
Transdimension Inc.
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For additional information, contact your Transdimension Regional Sales Representitive: INTERNET: http://www.transdimension.com E-MAIL: sales@transdimension.com, techsupport@transdimension.com Headquarters /N. America JAPAN: EUROPE: TransdimensionInc., 2 Venture, Irvine, CA 92618. Tel 949-727-2020, FAX 949-727-3232 Pete Todd, V.P. of Worldwide Sales: email: ptodd@transdimension.com TransdimensionInc., OYA Bldg. 5, 3 Chome-9-6, Nishi-shinjuku, Shinjuku-ku, Tokyo, Japan Tel. +81 (3) 5308 7525, FAX +81 (3) 5308 752, Masanori Sugane, e-mail: sugane@transdimension.com Transdimension Inc., 7 The Orchard, Hilton, Derbyshire, UK, DE65 5JF. Tel. +44 1283 730045, FAX +44 1283 730651, Neil Huntingdon, e-mail: nhungtingdon@transdimension.com
WorldWide Reps: See detailed listing for your area Transdimension representitive by viewing http://www.transdimension.com
THE DEVICE AND ITS DOCUMENTATION ARE PROVIDED "AS IS". TRANSDIMENSION HEREBY DISCLAIMS ALL WARRANTIES, EXPRESS, STATUTORY AND IMPLIED, APPLICABLE TO THE SOFTWARE AND ITS DOCUMENTATION AND ANY RELATED PRODUCTS, INCLUDING, BUT NOT LIMITED TO, ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE. TRANSDIMENSION ASSUMES NO LIABILITY FOR ANY ACT OR OMISSION OF LICENSEE. IN NO EVENT SHALL TRANSDIMENSION BE LIABLE FOR DIRECT, SPECIAL, INDIRECT, INCIDENTAL, PUNITIVE, EXEMPLARY OR CONSEQUENTIAL DAMAGES, INCLUDING, WITHOUT LIMITATION, LOSS OF PROFITS OR REVENUE, LOSS OF PRODUCTS, DATA OR ANY ASSOCIATED EQUIPMENT, COST OF CAPITAL, COST OF SUBSTITUTED EQUIPMENT OR PARTS, FACILITIES OR SERVICES, DOWN-TIME OR LABOR COSTS, EVEN IF TRANSDIMENSION HAS BEEN ADVISED OF THE POSSIBILITY THEREOF. The device and any related products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. Any such use and subsequent liabilities that may arise from such use are totally the responsibilities of the Licensee. Copyright (c) 2002, TransDimension Inc., All rights reserved. All product names are trademarks or registered trademarks of their respective owners. This document is subject to changes without notice.
All Rights Reserved Printed in U.S.A. February 2002
MU 3002, Rev. 1.0

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